1. Technical Field
Embodiments described herein relate to clock distribution networks in integrated circuits and more particularly to programmable clock drivers.
2. Description of the Related Art
Clock distribution networks account for a significant portion of overall power consumption in most high performance digital circuits today due to the large amounts of parasitic capacitance that is connected to the clock network. The switching frequency of the clock network, along with the need for a network that is robust to process and temperature variation, adds to the power consumption of the clock network.
A generalized view of the clock grid 100 can be seen in FIG. 1. The source of the clock signal 101 is typically a phased-lock loop (PLL), which is distributed over the processor core using a single, or a combination of clock trees, before a final stage of clock drivers drive a clock mesh. The clock grid 100 is divided into portions or tiles 103, which contain a clock mesh shown inside tile 103 coupled to the final driver 105. The size of the final driver 105 is a function of the effective load that the final clock driver drives on the mesh. The clock mesh allows for a robust clock grid whose clock skew and slew are less susceptible to process and temperature variation. The number of levels and physical distribution of the clock tree, and the number of tiles that make up the clock grid in various microprocessors or other integrated circuits, will vary. Nevertheless, many implementations of the global clock network are a variation of the approach illustrated in FIG. 1.
Most of the clock load in the distribution is found in the clock grid, and the final clock driver. Due to the difficulty in comprehensively modeling the impact of inductive effects in the clock grid, the impact of process variation, and varying temperature distribution during the various tasks performed by the processor, the clock grid tends to be overdesigned and overdriven to ensure that the grid will be robust to process and temperature variation. In most cases, overdriving the clock network does not provide additional performance benefit but is nonetheless required to provide a margin of safety. In addition, while this performance margin is desired in high performance microprocessor modes, the resulting power dissipation is often not warranted when the processor is operating in energy-efficient, low performance modes.